1. Field of the Invention
The present invention generally relates to semiconductor memory devices, and particularly relates to a content addressable memory.
2. Description of the Related Art
A Content addressable memory (hereinafter referred to as a CAM) is a memory device that receives data as an input, and outputs an address. A CAM detects data that matches input data within a memory area, and outputs an address at which the matched data is stored. The input data is referred to as an entry key, and the stored data are called entry data.
FIG. 1 is an example of a cell used in a CAM.
A CAM 10 of FIG. 1 includes NMOS transistors 11 through 16 and inverters 17 and 18. The inverters 17 and 18 together form a latch that stores therein one bit data. When the CAM 10 stores xe2x80x9c1xe2x80x9d therein, the data is latched such that a node N1 and a node N2 are xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d, respectively. When the CAM 10 stores xe2x80x9c0xe2x80x9d therein, the data is latched such that the node N1 and the node N2 are xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d, respectively. The storing of data is carried out by supplying the data to bit lines BL and /BL and activating a word line WL.
An entry key is provided through a search bus SB and /SB. When the entry key is xe2x80x9c1xe2x80x9d, the search bus lines SB and /SB are xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d, respectively. When the entry key is xe2x80x9c0xe2x80x9d, the search bus lines SB and /SB are xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d, respectively.
In an initial state, a match line ML is precharged to HIGH. An entry key is then supplied to the CAM 10 through the search bus SB and /SB. If a 0/1 data combination of the search bus SB and /SB matches a 0/1 data combination of the entry data stored in the CAM cell 10, the match line ML stays HIGH. If they do not match, the NMOS transistors 11 and 13 simultaneously become conductive, or the NMOS transistors 12 and 14 simultaneously become conductive, so that the match line ML is coupled to the ground to become LOW.
A plurality of CAM cells identical to the CAM cell 10 as described above are provided to store entry data comprised of a plurality of bits, and are connected to the same match line ML in parallel. This provision makes it possible to check a match/mismatch status of an entry key comprised of a plurality of bits.
FIG. 2 is an illustrative drawing showing a configuration in which a plurality of CAM cells 10 are connected to a common match line.
As shown in FIG. 2, a plurality of CAM cells 10 are connected to the same match line ML. If any one of the CAM cells 10 does not match an entry key, i.e., if there is a difference of even a single bit between the entry data and the entry key, the match line ML that has been precharged to HIGH in the initial state is coupled to the ground to be pulled down. If the entry data and the entry key match, the match line ML stays HIGH.
The match line ML is connected to a match line sense amplifier (MLSA) 20 and a match line precharge circuit 21. The match line sense amplifier 20 is mainly comprised of a differential amplifier, and detects the signal level of the match line ML by comparing the potential of the match line ML with a reference potential. The result of detection by the match line sense amplifier 20 is latched by a latch circuit 22 provided at a following stage. The match line precharge circuit 21 precharges the match line ML to a HIGH potential after the data detection by the match line sense amplifier 20 and the latching of data by the latch circuit 22. This completes preparation for a next data search.
FIG. 3 is a drawing showing voltage changes of the match line ML at the time of a data search.
As shown in FIG. 3, when a data search starts by comparing entry data with an entry key, the potential of the match line ML is brought down to the ground potential in the case of a data mismatch. In the case of a data match, however, the potential of the match line ML exhibits almost no change from the precharge potential. After the data detection by the match line precharge circuit 21 and the latching of data by the latch circuit 22, the match line precharge circuit 21 starts a precharge operation. Through this operation, the potential of the match line ML is set to the precharge potential.
In the content addressable memory that operates as described above, the precharging of a match line cannot be carried out until the detection of data by the match line precharge circuit 21 and the latching of data by the latch circuit 22 are completed. Because of this, the speed of a search is limited by the time length required by the detection of data and the latching of data, which makes it difficult to achieve a high-speed search.
Accordingly, there is a need for a content addressable memory that operates at high speed by advancing the timing of a precharge operation.
It is a general object of the present invention to provide a content addressable memory device that substantially obviates one or more of the problems caused by the limitations and disadvantages of the related art.
Features and advantages of the present invention will be set forth in the description which follows, and in part will become apparent from the description and the accompanying drawings, or may be learned by practice of the invention according to the teachings provided in the description. Objects as well as other features and advantages of the present invention will be realized and attained by a content addressable memory device particularly pointed out in the specification in such full, clear, concise, and exact terms as to enable a person having ordinary skill in the art to practice the invention.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, a content addressable memory device according to the present invention includes a match line having a potential thereof changed according to whether data of a memory cell matches a search key of a search bus, a precharge circuit which precharges the match line, a sample-and-hold circuit which samples and holds the potential of the match line, and a detection circuit which detects the potential held by the sample-and-hold circuit.
In the content addressable memory device as described above, the potential of the match line is sampled and held by the sample-and-hold circuit, so that the precharge circuit can precharge the match line during the hold operation of the sample-and-hold circuit after an end of the sample operation of the sample-and-hold circuit. Accordingly, the present invention can advance the timing of a precharge operation relative to the related-art precharge timing, thereby increasing the operation speed of the content addressable memory device.
According to another aspect of the present invention, a method of precharging in a content addressable memory device includes the steps of sampling and holding a potential of a match line that changes according to whether data of a memory cell matches a search key of a search bus, detecting the sampled and held potential, and precharging the match line to a predetermined potential concurrently with the detecting of the sampled and held potential.
Other objects and further features of the present invention will be apparent from the following detailed description when read in conjunction with the accompanying drawings.